1. Field of the Invention
This invention relates to a method of fabrication of a semiconductor device, and more particularly to a method of formation of isolation trenches in a very small semiconductor device of a submicron size.
2. Description of the Prior Art
One of the prior art methods of formation of an isolation trench in a semiconductor device is described with reference to FIG. 1A to 1E.
As illustrated in FIG. 1A, a thick gate oxide film 2 of about 10-25 nm is first formed on an area of a P-type silicon substrate 1 including a memory cell formation area. In succession, an entire substrate is coated as a first insulating film with a thick silicon oxide film of about 100-150 nm for example. Then, a 0.4-0.6 .mu.m wide opening is formed using a resist film 5 only at a portion where a device isolation scheduled area 6 is formed. A first insulating film 4, a polycrystalline silicon film 3, and a gate oxide film 2 are anisotropically etched successively to selectively expose a P-type silicon substrate 1. Then, after the resist film 5 is removed as illustrated in FIG. 1B, etching is carried out with the first insulating film 4 taken as a mask to form a 0.5-1.5.mu.m deep trench 7. Further, as illustrated in FIG. 1C, a non-doped silicon oxide film (second insulating film 8) for example, which is shown in a dry etching rate than a third insulating film to be formed later such as a BPSG, is deposited into an about 100-200 nm thickness, and in succession a BPSG film (borophospho silicate glass film) for example as the third insulating film 9 is deposited into a 1.0-2.0 .mu.m thickness, in order to completely bury the trench, which BPSG film is in turn re-flowed by an approximately 850.degree.-950.degree. C. heat treatment to complete the trench and simultaneously flatten the surface. Successively, as illustrated in FIG. 1D, etching-back is applied using the polycrystalline silicon film 8 as a stopper. The etching-back ideally being completed as the top surface of the insulating film 9 is coincident with the top surface of the polycrystalline silicon film 3 as the stopper. Over-etching is however likely to occur owing to the difficulty in controlling the etching-back, which can produce an indentation 10. The indentation 10 is however through the third insulating film 9, and the second insulating film 8 is etched more slowly than the third insulating film 9, and hence in the worst case the etching-back is terminated above the gate oxide film 2. The substrate is prevented from being exposed along the sides of the trench.
Further, as illustrated in FIG. 1E, a silicide wiring 11 is formed by depositing a tungsten silicide film over the entire surface of the semiconductor substrate and selectively removing part of the same, and a source-drain region is formed by ion doping. A MOS transistor is successfully formed which includes a device isolation trench 7A and a polycide gate electrode formed in a self-alignment manner to the former.
In the prior art method of forming the device isolation trench, the third insulating film 9 is unlikely to be controlled in the uniformity thereof in a wafer surface addditionally to the difficulty of the control of the etching-back, and hence variations of the thickness of the third insulating film 9 sometimes amount to about 10%.
Accordingly, deposition of the film 9 of even 1.3 .mu.m causes a film thickness difference in the wafer surface to become 130 nm, and an indentation to completely etch back the film 9 in the wafer surface causes overetching depending upon the location thereof in the wafer surface. Thereupon, provided the etching-back is carried out at a location of the third insulating film 9 where it is originally thinner, the second insulating film might also be overetched to expose the substrate. This might produce short-circuitting of the silicide wiring with the conductive film lowering the yield of the semiconductor device.